Several trends presently exist in the semiconductor and electronics industry. Devices are continually getting smaller, faster and requiring less power. A reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as their primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, that are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
The process of manufacturing integrated circuits typically consists of more than a hundred steps, during which hundreds or thousands of copies of an integrated circuit can be formed on a single wafer. This process can create electrically active regions in and on the semiconductor wafer surface. In MOS transistors, for example, a gate structure containing conductive material(s) is created, that can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor. The source and drain regions facilitate this conductance by virtue of containing a majority of positively doped (p) or negatively doped (n) materials.
As device sizes continue to shrink, however, capacitive effects may become noticeable and/or problematic. There are a number of extrinsic and intrinsic capacitances associated with a MOS transistor. For example, ion implantation is utilized to create the conductive source and drain regions, as well as conductive source and drain extension regions in the transistor. Such implantation may also be utilized in creating the gate structure. The source, drain and extension regions are generally formed within the semiconductor substrate adjacent the gate structure. Other layers and/or features may also be formed on the semiconductor substrate adjacent the gate structure. One or more of these items and/or features may not, however, be conductive and may instead have a dielectric constant (k) that is not low.
One type of feature that is commonly formed adjacent the gate structure upon the semiconductor substrate is a sidewall spacer. Sidewall spacers are generally utilized to block dopants from being implanted into a portion of the semiconductor substrate during a source/drain implant. The spacers thus direct the implants into desired locations within the semiconductor substrate. Sidewall spacers are generally formed out of materials that do not, however, have a low dielectric constant. As such, parasitic capacitance can develop between the conductive gate structure, non conductive dielectric sidewall spacer and the conductive drain as these items can act as “plates” of a capacitor. A capacitive charge can thus build-up between these “plates” when a signal comes through the transistor. Such a charge slows down the speed, and more particularly the switching speed, of the transistor as this potential has to be discharged before the transistor can switch or toggle again. This, obviously, is deleterious to the desired operation of the transistor.
The value of such parasitic capacitance depends, among other things, upon the degree of separation between the layers or “plates” as well as the dielectric constant (k) of the material out of which the sidewall spacer separating the conductive gate structure and conductive drain is made. In particular, such capacitance increases as the distance between the plates decreases and increases as the dielectric constant of the sidewall spacer increases. Accordingly, as scaling occurs and features are shrunk and the “plates” are brought closer together, parasitic capacitance can increase. This capacitance can be maintained or reduced, however, by altering (e.g., reducing) the dielectric constant of the sidewall spacer. However, conventionally, low-k materials can not be utilized for sidewall spacers as they cannot withstand certain processing conditions. Low-k materials may not, for example, be able to withstand subsequent cleaning activities. As such, low-k spacers may become damaged during such cleaning processes, and the operation of the transistor can thereby be compromised. Similarly, low-k materials may become damaged or deformed during an etching process, rendering the low-k spacers, at least partially, ineffective to prevent dopants from being implanted into undesired locations within the substrate, and improperly or incorrectly placed implants can degrade the operation of the transistor.
Accordingly, improved techniques for fabricating densely packed semiconductor devices would be desirable. More particularly, it would be desirable to fabricate semiconductor devices in a manner that allows for low-k sidewall spacers to be utilized such that parasitic capacitances are mitigated and faster switching speeds are thereby facilitated.